1. Field of the Invention
The present invention relates to a data transmission apparatus and a data receiving apparatus for the same, especially, relates to a technique to transmit data through a transmission line having a pair of transmission line.
2. Description of the Related Art
As a semiconductor technology advances, a data processing apparatus (computer) mounting high density semiconductor integrated circuits with high speed operation is widespread. In such a data processing apparatus, the apparatus is demanded to operate at higher processing speed. Also, a mobile terminal is also widespread, which is configured of high density semiconductor integrated circuits. The semiconductor integrated circuit for the mobile terminal is demanded not only to operate at a high speed but also lower power consumption. In such a semiconductor integrated circuit, various techniques have been proposed to improve a data processing speed. One of the techniques is to speed up a transfer speed of data transmitted and received between the semiconductor integrated circuits.
For instance, an interface circuit is disclosed in Japanese Laid Open Patent Applications (JP-P2001-53598A, and JP-P2003-348176; first and second conventional examples). In the first and second conventional examples, a data outputted from a semiconductor integrated circuit is supplied to another semiconductor integrated circuit through a transmission line. A transmitter circuit is contained in the semiconductor integrated circuit on the data transmission side. A receiver circuit is contained in the semiconductor integrated circuit on the data reception side.
FIG. 1 is a circuit diagram showing a configuration of a receiver circuit described in the above-mentioned first conventional example. As shown in FIG. 1, the receiver circuit 100, which is equivalent to the receiver section 51 in the first conventional example, is configured of a N-channel transistor 101, a N-channel transistor 102, a first receiving section 110, a second receiving section 120, a flip-flop 130, and an inverter 103.
Gates of the N-channel transistor 101 and the N-channel transistor 102 are connected to each other. The N-channel transistor 101 is provided between a node 141 and a ground potential GND. The N-channel transistor 101 is connected with the first receiving section 110 through the node 141. Also, the N-channel transistor 101 is connected with the second receiving section 120 through the node 141. Similarly, the N-channel transistor 102 is provided between a node 142 and the ground potential GND. The N-channel transistor 102 is connected with the first receiving section 110 and the second receiving section 120 through the node 142. The first receiving section 110 includes a first P-channel transistor 111 and a second P-channel transistor 112, a first N-channel transistor 113, and a second N-channel transistor 114. Similarly, the second receiving section 120 includes a third P-channel transistor 121, a fourth P-channel transistor 122, a third N-channel transistor 123, and a N-channel transistor 124. Moreover, the flip-flop 130 includes a first NAND circuit 131 and a second NAND circuit 132. The first NAND circuit 131 and second NAND circuit 132 are connected each other so as to configure the RS latch circuit.
Moreover, a first input terminal 104 and a second input terminal 105 are connected with a transmitter circuit (not shown) through two transmission lines. In addition, a bias terminal 106 is connected to a gate of each of the first N-channel transistor 113, the second N-channel transistor 114, the third N-channel transistor 123, and the fourth N-channel transistor 124. A predetermined voltage is supplied from the bias terminal 106 to each of the gates of the above-mentioned transistors. The transmitter circuit sets the first input terminal 104 or the second input terminal 105 to the ground potential or a state of a high impedance (hereafter, to be referred to as a floating voltage) based on a signal level of a transmission data. When one of the first input terminal 104 and the second input terminal 105 is set to the ground potential, the other terminal is set to the floating voltage.
When the first input terminal 104 is in the ground potential, and the second input terminal 105 is in the floating voltage, the first N-channel transistor 113 and the third N-channel transistor 123 are turned on. Therefore, the node 125 becomes a low level. At this time, the second N-channel transistor 114 and the fourth N-channel transistor 125 are turned off. Therefore, a node 115 becomes a high level. Also, when the first input terminal 104 is in the floating voltage, and the second input terminal 105 is in the ground potential, the first N-channel transistor 113 and the third N-channel transistor 123 are turned off. Therefore, the node 125 becomes the high level. At this time, the second N-channel transistor 114 and the fourth N-channel transistor 125 are turned on. Therefore, the node 115 becomes the low level. The flip-flop 130 stores an output signal based on the levels of the nodes 115 and 125, and outputs the stored signal from the output terminal 107 through the inverter 103.
The first N-channel transistor 113 and the third N-channel transistor 123 or the second N-channel transistor 114 and the fourth N-channel transistor 124 supply electric current to the N-channel transistor 101 or the N-channel transistor 102 even if the first input terminal 104 or the second input terminal 105 is set to the floating voltage. For this reason, the first input terminal 104 or the second input terminal 105 is set to the potential of 50 to 200 mV even in a floating state. A voltage at this time is an amplitude voltage on the transmission line. In this case, the electric current flowing to the first N-channel transistor 113 and the third N-channel transistor 123 or the second N-channel transistor 114 and the fourth N-channel transistor 124 depends on gate-source voltages of the first N-channel transistor 113 and the third N-channel transistor 123 or the second N-channel transistor 114 and the fourth N-channel transistor 124 (hereinafter, to be referred to as a voltage GS113, a voltage GS114, a voltage GS123, and a voltage GS124, respectively).
In a word, the electric current flowing to the first N-channel transistor 113 and the third N-channel transistor 123 or the second N-channel transistor 114 and the fourth N-channel transistor 124 depends on the deference between the potential of the first input terminal 104 or the second input terminal 105 and the potential of the bias terminal 106. This is similar even when the first input terminal 104 or the second input terminal 105 is set to the ground potential. The amplitude voltages of the first input terminal 104 and the second input terminal 105 in the receiver circuit 100 depend on a resistance of the N-channel transistor 101, a resistance of the N-channel transistor 102, and a resistance from an output transistor of the transmitter circuit to the first input terminal 104 or the second input terminal 105.
For instance, it is supposed that a resistance from the output transistor of the transmitter circuit to the first input terminal 104 (or the second input terminal 105) is 200Ω. Also, it is supposed that a current value flowing from the second input terminal 105 to the transmitter circuit in response to the signal from the transmitter circuit is 200 μA. In this case, the second input terminal 105 has a voltage in a floating state higher by 40 mV (=200Ω*200 μA) than the ground potential. The voltage of the second input terminal 105 when the transistor is turned off is determined based on the electric resistance of the N-channel transistor 102 and the electric current flowing to the N-channel transistor 102 in the receiver circuit 100 shown in FIG. 1. Therefore, the amplitude voltage at the second input terminal 105 is changed depending on the resistances of the N-channel transistor 101 and N-channel transistor 102, and the resistance from the transistor of the transmitter circuit to the first input terminal 104 (or the second input terminal 105).
Even if the first input terminal 104 (or the second input terminal 105) is set to the ground potential, the voltage at the first input terminal 104 (or the second input terminal 105) is higher by a slight voltage than the ground potential due to the ON resistance of the transistor of the transmitter circuit, the impedance of the transmission line, and the like (hereinafter, this voltage is referred to as a floating voltage). Thus, the voltages GS113 to GS124 are influenced by the deviation of the floating voltage. For this reason, the power consumption of the receiver circuit 100 results in being changed.
Further, the voltage difference of the first input terminal 104 (or the second input terminal 105), as the amplitude voltage of the transmission line, is changed due to the floating voltage. The change of power consumption is a problem to a mobile terminal in which low power consumption is essentially required. Also, the change of the amplitude voltage on the transmission line causes instability in the high speed transmitting operation. Moreover, if the ground potential in the transmitter circuit rises higher than the ground potential of the receiver circuit for some reasons, the amplitude voltage on the transmission line becomes small. For this reason, some measure might be occasionally needed, such as widening the gate width of the transistor of the transmitter circuit. In this case, it is necessary to enlarge the layout area, which restricts the high density integration. Moreover, it is not preferable that the ON resistance results in being lowered extremely for the impedance matching with the transmission line.
FIG. 2 is a circuit diagram showing a configuration of the transmitter circuit shown in the above-mentioned second conventional example. As shown in FIG. 2, a transmitter circuit 200 (equivalent to a transmitter 41 in the above-mentioned second conventional example) includes an inverter 201, an inverter 202, a first N-channel transistor 203, a second N-channel transistor 204, and a third N-channel transistor 205. In the transmitter circuit 200, a complementary signal output is connected through the third N-channel transistor 203. The third N-channel transistor 205 is turned on when the signal is transmitted, and is turned off when the signal is not transmitted. In this way, the amplitude voltage of the complementary signal is made small, and a delay is shortened when the signal is transmitted from the transmitter circuit to the receiver circuit.
In the high-speed transmission line shown in FIG. 2, transistors are connected between the complementary signal outputs on the transmitter circuit side. As shown in FIG. 2, in the transmitter circuit 200, the third N-channel transistor 205 is added to the transmitter circuit. It is preferable that the configuration of the transmitter circuit is simple. However, the configuration of the transmitter circuit 200 makes the simplification difficult. Moreover, the receiver circuit and the transmitter circuit are independent products respectively. Therefore, considering that some modification may be required on the transmitter circuit, it is desirable that the configuration has flexibility for the modification.